A Review on VHDL Implementation for Adaptive Finite Impulse Response filter and its novel applications using Systolic Architecture

The evolution of computer and Internet has brought demand for powerful and high speed data processing. In such complex environment, the conventional methods of performing matrix multiplications are not suitable to obtain the perfect solution. To handle above addressed issue, parallel computing is proposed as a solution to the contradiction. The DLMS adaptive algorithm minimizes approximately the mean square error by recursively altering the weight vector at each sampling instance. This project demonstrates an effective design for adaptive filter using Systolic architecture, synthesized and simulated on Xilinx ISE 12.1 Project navigator tool in very high speed integrated circuit hardware description language (VHDL) using Systolic Architecture on Reconfigurable Systems (RS) like Field Programmable Gate Arrays (FPGAs). Here, the systolic architecture increases the computing speed by combining the concept of parallel processing and pipelining into a single concept.